#ifndef enc28j60H #define enc28j60H /* * Exported functions * ============================================================================ */ /* network buffer access */ #define NB_SEEK_SET 0 #define NB_SEEK_CUR 1 #define NB_SEEK_ABS 2 /* absolute seek, no buffer wrapping */ void delay (unsigned int us); /* read */ extern void netbuf_rd_seek(int pos, unsigned char origin); extern unsigned int netbuf_rd_tell(void); extern unsigned char netbuf_getc(void); extern void netbuf_read(void *buffer, int len); extern void netbuf_skip(int len); /* write */ extern void netbuf_wr_seek(int pos, unsigned char origin); extern unsigned int netbuf_wr_tell(void); extern void netbuf_putc(unsigned char data); extern void netbuf_write(void *buffer, int len); extern void netbuf_fill(unsigned char data, int len); extern void netbuf_copy(unsigned int len); extern void netbuf_close(void); /* network device init */ extern void nic_init(void); /* packet reception */ extern unsigned int nic_rx(void); extern void nic_rx_free(void); /* packet transmission */ extern unsigned int nic_tx_alloc(unsigned int *pt); extern void nic_tx(unsigned int len); /* network link status */ extern unsigned int nic_link(void); /* register access, just for debugging purposes */ #ifdef DEBUG extern void enc28_ctlreg_wr(unsigned char reg, unsigned char data); extern unsigned char enc28_ctlreg_rd(unsigned char reg); extern void enc28_ctlreg_set(unsigned char reg, unsigned char data); extern void enc28_ctlreg_clr(unsigned char reg, unsigned char data); extern void enc28_ctlreg_wr16(unsigned char reg, unsigned int data); extern unsigned int enc28_ctlreg_rd16(unsigned char reg); extern void enc28_phyreg_wr(unsigned char reg, unsigned int data); extern unsigned int enc28_phyreg_rd(unsigned char reg); #endif //větve - predelasno pro Juranka #define V0 PORTBbits.RB1 #define V1 PORTBbits.RB2 #define V2 PORTBbits.RB3 #define V3 PORTBbits.RB4 #define V4 PORTBbits.RB5 // // #define LEDCERV PORTCbits.RC13 /* SPI signals */ #define SPI_nCS PORTBbits.RB9 #define SPI_SCK PORTBbits.RB8 #define SPI_MOSI PORTBbits.RB7 #define SPI_MISO PORTBbits.RB6 /* total buffer size */ #define ENC28_BUFSIZE 0x2000 /* buffer allocation, receive buffer has to start at 0 - silicon errata no. 3 */ #define ENC28_RXBUF_START 0x0000 #define ENC28_RXBUF_END 0x19ff #define ENC28_RXBUF_LEN (ENC28_RXBUF_END-ENC28_RXBUF_START+1) #define ENC28_TXBUF_START (ENC28_RXBUF_END+1) /* constants */ #define MAX_FRAMELEN 1518 /* * ENC28J60 Control Registers * Control register definitions are a combination of address, * bank number, and Ethernet/MAC/PHY indicator bits. * - Register address (bits 0-4) * - Bank number (bits 5-6) * - MAC/PHY indicator (bit 7) */ /* masks for adress, bank a SPI read delay for MREGS */ #define ENC28_ADDR_MASK 0x1F #define ENC28_BANK_MASK 0x60 #define ENC28_SPRD_MASK 0x80 /* bank select values */ #define ENC28_BANK0 0x00 #define ENC28_BANK1 0x20 #define ENC28_BANK2 0x40 #define ENC28_BANK3 0x60 /* common registers */ #define EIE 0x1B #define EIR 0x1C #define ESTAT 0x1D #define ECON2 0x1E #define ECON1 0x1F /* bank 0 */ #define ERDPTL (0x00|ENC28_BANK0) #define ERDPTH (0x01|ENC28_BANK0) #define EWRPTL (0x02|ENC28_BANK0) #define EWRPTH (0x03|ENC28_BANK0) #define ETXSTL (0x04|ENC28_BANK0) #define ETXSTH (0x05|ENC28_BANK0) #define ETXNDL (0x06|ENC28_BANK0) #define ETXNDH (0x07|ENC28_BANK0) #define ERXSTL (0x08|ENC28_BANK0) #define ERXSTH (0x09|ENC28_BANK0) #define ERXNDL (0x0A|ENC28_BANK0) #define ERXNDH (0x0B|ENC28_BANK0) #define ERXRDPTL (0x0C|ENC28_BANK0) #define ERXRDPTH (0x0D|ENC28_BANK0) #define ERXWRPTL (0x0E|ENC28_BANK0) #define ERXWRPTH (0x0F|ENC28_BANK0) #define EDMASTL (0x10|ENC28_BANK0) #define EDMASTH (0x11|ENC28_BANK0) #define EDMANDL (0x12|ENC28_BANK0) #define EDMANDH (0x13|ENC28_BANK0) #define EDMADSTL (0x14|ENC28_BANK0) #define EDMADSTH (0x15|ENC28_BANK0) #define EDMACSL (0x16|ENC28_BANK0) #define EDMACSH (0x17|ENC28_BANK0) /* bank 1 */ #define EHT0 (0x00|ENC28_BANK1) #define EHT1 (0x01|ENC28_BANK1) #define EHT2 (0x02|ENC28_BANK1) #define EHT3 (0x03|ENC28_BANK1) #define EHT4 (0x04|ENC28_BANK1) #define EHT5 (0x05|ENC28_BANK1) #define EHT6 (0x06|ENC28_BANK1) #define EHT7 (0x07|ENC28_BANK1) #define EPMM0 (0x08|ENC28_BANK1) #define EPMM1 (0x09|ENC28_BANK1) #define EPMM2 (0x0A|ENC28_BANK1) #define EPMM3 (0x0B|ENC28_BANK1) #define EPMM4 (0x0C|ENC28_BANK1) #define EPMM5 (0x0D|ENC28_BANK1) #define EPMM6 (0x0E|ENC28_BANK1) #define EPMM7 (0x0F|ENC28_BANK1) #define EPMCSL (0x10|ENC28_BANK1) #define EPMCSH (0x11|ENC28_BANK1) #define EPMOL (0x14|ENC28_BANK1) #define EPMOH (0x15|ENC28_BANK1) #define EWOLIE (0x16|ENC28_BANK1) #define EWOLIR (0x17|ENC28_BANK1) #define ERXFCON (0x18|ENC28_BANK1) #define EPKTCNT (0x19|ENC28_BANK1) /* bank 2 */ #define MACON1 (0x00|ENC28_BANK2|ENC28_SPRD_MASK) /* #define MACON2 (0x01|ENC28_BANK2|ENC28_SPRD_MASK) */ #define MACON3 (0x02|ENC28_BANK2|ENC28_SPRD_MASK) #define MACON4 (0x03|ENC28_BANK2|ENC28_SPRD_MASK) #define MABBIPG (0x04|ENC28_BANK2|ENC28_SPRD_MASK) #define MAIPGL (0x06|ENC28_BANK2|ENC28_SPRD_MASK) #define MAIPGH (0x07|ENC28_BANK2|ENC28_SPRD_MASK) #define MACLCON1 (0x08|ENC28_BANK2|ENC28_SPRD_MASK) #define MACLCON2 (0x09|ENC28_BANK2|ENC28_SPRD_MASK) #define MAMXFLL (0x0A|ENC28_BANK2|ENC28_SPRD_MASK) #define MAMXFLH (0x0B|ENC28_BANK2|ENC28_SPRD_MASK) #define MAPHSUP (0x0D|ENC28_BANK2|ENC28_SPRD_MASK) #define MICON (0x11|ENC28_BANK2|ENC28_SPRD_MASK) #define MICMD (0x12|ENC28_BANK2|ENC28_SPRD_MASK) #define MIREGADR (0x14|ENC28_BANK2|ENC28_SPRD_MASK) #define MIWRL (0x16|ENC28_BANK2|ENC28_SPRD_MASK) #define MIWRH (0x17|ENC28_BANK2|ENC28_SPRD_MASK) #define MIRDL (0x18|ENC28_BANK2|ENC28_SPRD_MASK) #define MIRDH (0x19|ENC28_BANK2|ENC28_SPRD_MASK) /* bank 3 */ #define MAADR5 (0x00|ENC28_BANK3|ENC28_SPRD_MASK) #define MAADR6 (0x01|ENC28_BANK3|ENC28_SPRD_MASK) #define MAADR3 (0x02|ENC28_BANK3|ENC28_SPRD_MASK) #define MAADR4 (0x03|ENC28_BANK3|ENC28_SPRD_MASK) #define MAADR1 (0x04|ENC28_BANK3|ENC28_SPRD_MASK) #define MAADR2 (0x05|ENC28_BANK3|ENC28_SPRD_MASK) #define EBSTSD (0x06|ENC28_BANK3) #define EBSTCON (0x07|ENC28_BANK3) #define EBSTCSL (0x08|ENC28_BANK3) #define EBSTCSH (0x09|ENC28_BANK3) #define MISTAT (0x0A|ENC28_BANK3|ENC28_SPRD_MASK) #define EREVID (0x12|ENC28_BANK3) #define ECOCON (0x15|ENC28_BANK3) #define EFLOCON (0x17|ENC28_BANK3) #define EPAUSL (0x18|ENC28_BANK3) #define EPAUSH (0x19|ENC28_BANK3) /* PHY registers, indirect access */ #define PHCON1 0x00 #define PHSTAT1 0x01 #define PHHID1 0x02 #define PHHID2 0x03 #define PHCON2 0x10 #define PHSTAT2 0x11 #define PHIE 0x12 #define PHIR 0x13 #define PHLCON 0x14 /* EIE bits */ #define EIE_INTIE 0x80 #define EIE_PKTIE 0x40 #define EIE_DMAIE 0x20 #define EIE_LINKIE 0x10 #define EIE_TXIE 0x08 #define EIE_WOLIE 0x04 #define EIE_TXERIE 0x02 #define EIE_RXERIE 0x01 /* EIR bits */ #define EIR_PKTIF 0x40 #define EIR_DMAIF 0x20 #define EIR_LINKIF 0x10 #define EIR_TXIF 0x08 #define EIR_WOLIF 0x04 #define EIR_TXERIF 0x02 #define EIR_RXERIF 0x01 /* ESTAT bits */ #define ESTAT_INT 0x80 #define ESTAT_BUFER 0x40 #define ESTAT_LATECOL 0x10 #define ESTAT_RXBUSY 0x04 #define ESTAT_TXABRT 0x02 #define ESTAT_CLKRDY 0x01 /* ECON2 bits */ #define ECON2_AUTOINC 0x80 #define ECON2_PKTDEC 0x40 #define ECON2_PWRSV 0x20 #define ECON2_VRPS 0x08 /* ECON1 bits */ #define ECON1_TXRST 0x80 #define ECON1_RXRST 0x40 #define ECON1_DMAST 0x20 #define ECON1_CSUMEN 0x10 #define ECON1_TXRTS 0x08 #define ECON1_RXEN 0x04 #define ECON1_BSEL1 0x02 #define ECON1_BSEL0 0x01 /* MACON1 bits */ #define MACON1_LOOPBK 0x10 #define MACON1_TXPAUS 0x08 #define MACON1_RXPAUS 0x04 #define MACON1_PASSALL 0x02 #define MACON1_MARXEN 0x01 /* MACON2 bits */ #define MACON2_MARST 0x80 #define MACON2_RNDRST 0x40 #define MACON2_MARXRST 0x08 #define MACON2_RFUNRST 0x04 #define MACON2_MATXRST 0x02 #define MACON2_TFUNRST 0x01 /* MACON3 bits */ #define MACON3_PADCFG2 0x80 #define MACON3_PADCFG1 0x40 #define MACON3_PADCFG0 0x20 #define MACON3_TXCRCEN 0x10 #define MACON3_PHDRLEN 0x08 #define MACON3_HFRMLEN 0x04 #define MACON3_FRMLNEN 0x02 #define MACON3_FULDPX 0x01 /* MICMD bits */ #define MICMD_MIISCAN 0x02 #define MICMD_MIIRD 0x01 /* MISTAT bits */ #define MISTAT_NVALID 0x04 #define MISTAT_SCAN 0x02 #define MISTAT_BUSY 0x01 /* PHCON1 bits */ #define PHCON1_PRST 0x8000 #define PHCON1_PLOOPBK 0x4000 #define PHCON1_PPWRSV 0x0800 #define PHCON1_PDPXMD 0x0100 /* PHSTAT1 bits */ #define PHSTAT1_PFDPX 0x1000 #define PHSTAT1_PHDPX 0x0800 #define PHSTAT1_LLSTAT 0x0004 #define PHSTAT1_JBSTAT 0x0002 /* PHCON2 bits */ #define PHCON2_FRCLINK 0x4000 #define PHCON2_TXDIS 0x2000 #define PHCON2_JABBER 0x0400 #define PHCON2_HDLDIS 0x0100 /* PKTCTRL bits */ #define PKTCTRL_PHUGEEN 0x08 #define PKTCTRL_PPADEN 0x04 #define PKTCTRL_PCRCEN 0x02 #define PKTCTRL_POVERRIDE 0x01 /* SPI commands */ #define ENC28_RCR 0x00 #define ENC28_RBM 0x3A #define ENC28_WCR 0x40 #define ENC28_WBM 0x7A #define ENC28_BFS 0x80 #define ENC28_BFC 0xA0 #define ENC28_SRC 0xFF #ifdef ETHADDR0 // MAC address for this interface #define ENC28J60_MAC0 ETHADDR0 #define ENC28J60_MAC1 ETHADDR1 #define ENC28J60_MAC2 ETHADDR2 #define ENC28J60_MAC3 ETHADDR3 #define ENC28J60_MAC4 ETHADDR4 #define ENC28J60_MAC5 ETHADDR5 #else #define ENC28J60_MAC0 0x00 #define ENC28J60_MAC1 0xbc #define ENC28J60_MAC2 0x6f #define ENC28J60_MAC3 0x55 #define ENC28J60_MAC4 0x1c #define ENC28J60_MAC5 0xc4 //tady bylo c3 u modulu 192.168.1.221 #endif #endif