BANK  0 BANK 1 BANK 2 BANK 3 BANK 4 BANK  5
0            
           
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
           
B            
C PORTA TRISA LATA ANSELA WPUA ODCONA
D PORTB TRISB LATB ANSELB WPUB ODCONB
E PORTC TRISC LATC ANSELC WPUC ODCONC
F -- -- -- -- -- --
10 -- -- -- -- -- --
11 PIR1 PIE1 CM1CON0 PMADRL SSP1BUF CCPRL
12 PIR2 PIE2 CM1CON1 PMADRH SSP1ADD CCPR1H
13 PIR3 PIE3 CM2CON0 PMDATL SSP1MSK CCP1CON
14 -- -- CM2CON1 PMDATH SSP1STAT --
15 TMR0 OPTION_REG CMOUT PMCON1 SSP1CON --
16 TMR1L PCON BORCON PMCON2 SSP1CON2 --
17 TMR1H WDTCON FVRCON -- SSP1CON3 --
18 T1CON OSCTUNE DAC1CON0 -- -- CCPR2L
19 T1GCON OSCCON DAC1CONN1 RC1REG -- CCPR2H
1A TMR2 OSCSTAT -- TX1REGG -- CCP2CON
1B PR2 ADRESL -- SP1BRGL -- --
1C T2CON ADRESH ZCD1CON SP1BRGH -- --
1D -- ADCON0 -- RC1STA -- --
1E -- ADCON1 -- TXSTA -- CCPTMRS
1F -- ADCON2 -- BAUD1CON -- --
20            
           
General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose
Registers Registers Registers Registers Registers Registers
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
           
6F            
70            
           
Common RAM Accesses Accesses Accesses Accesses Accesses
           
7F